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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES 5 V Stereo Audio System with 3.3 V Tolerant Digital Interface Supports up to 96 kHz Sample Rates 192 kHz Sample Rate Available on One DAC Supports 16-/20-/24-Bit Word Lengths Multibit Sigma-Delta Modulators with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DACs--Least Sensitive to Jitter Differential Output for Optimum Performance ADCs: -92 dB THD + N, 100 dB SNR, and Dynamic Range DACs: -95 dB THD + N, 110 dB SNR, and Dynamic Range On-Chip Volume Controls per Channel with 1024-Step Linear Scale DAC and ADC Software Controllable Clickless Mutes Digital De-Emphasis Processing
2 ADC, 8 DAC, 96 kHz, 24-Bit - Codec AD1835
Supports 256 fS, 512 fS, and 768 fS Master Mode Clocks Power-Down Mode Plus Soft Power-Down Mode Flexible Serial Data Port with Right-Justified, LeftJustified, I2S-Compatible, and DSP Serial Port Modes TDM Interface Mode Supports 8 In/8 Out Using a Single SHARC SPORT 52-Lead MQFP Plastic Package APPLICATIONS DVD Video and Audio Players Home Theater Systems Automotive Audio Systems Audio/Visual Receivers Digital Audio Effects Processors PRODUCT OVERVIEW
The AD1835 is a high-performance, single-chip codec featuring four stereo DACs and one stereo ADC. Each DAC comprises a high-performance digital interpolation filter, a multibit sigmadelta modulator featuring Analog Devices' patented technology,
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FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT MCLK PD/RST M/S AVDD AVDD
DLRCLK DBCLK DSDATA1 DSDATA2 DSDATA3 DSDATA4 SERIAL DATA I/O PORT
CONTROL PORT VOLUME VOLUME VOLUME VOLUME
CLOCK DIGITAL FILTER DAC OUTLP1 OUTLN1 OUTRP1 OUTRN1 OUTLP2 OUTLN2 OUTRP2 OUTRN2 OUTLP3 OUTLN3 OUTRP3 OUTRN3 OUTLP4 OUTLN4 OUTRP4 OUTRN4 FILTD FILTR
DIGITAL FILTER
DAC
ADCLP ADCLN
ADC
DIGITAL FILTER
VOLUME VOLUME VOLUME
DIGITAL FILTER
DAC
ADCRP ADCRN
ADC
DIGITAL FILTER
VOLUME
DIGITAL FILTER
DAC
VREF DGND DGND AGND AGND AGND AGND
SHARC is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD1835-SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AVDD, DVDD) . . . . . . . . . . . . . . . . . . . . . . . . Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAC Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Sample Rate (fS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measurement Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Load Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.0 V 25C 12.288 MHz, (256 fS Mode) 1.0078125 kHz, -1 dBFS (Full Scale) 1.0078125 kHz, 0 dBFS (Full Scale) 48 kHz 20 Hz to 20 kHz 24 Bits 100 pF 47 k
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Dynamic Range (20 Hz to 20 kHz, -60 dB Input) No Filter A-Weighted Total Harmonic Distortion + Noise (THD + N) Interchannel Isolation Interchannel Gain Mismatch Analog Inputs Differential Input Range ( Full Scale) Common-Mode Input Volts Input Impedance Input Capacitance VREF DC Accuracy Gain Error Gain Drift Crosstalk (EIAJ Method) DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Dynamic Range (20 Hz to 20 kHz, -60 dBFS Input) No Filter With A-Weighted Filter Total Harmonic Distortion + Noise Interchannel Isolation DC Accuracy Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ method) Interchannel Phase Deviation Volume Control Step Size (1023 Linear Steps) Volume Control Range (Max Attenuation) Mute Attenuation De-Emphasis Gain Error Full-Scale Output Voltage at Each Pin (Single-Ended) Output Resistance at Each Pin Common-Mode Output Volts ADC DECIMATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay Min Typ 24 100 101 103 105 -93 100 0.01 Max Unit Bits dB dB dB dB dB V V k pF V % ppm/C dB
-88.5
-2.828 2.25 4 15 2.25 +5 TBD TBD
+2.828
103 105
105 108 -95 100 4.0 0.01 150 -120 0.1 0.098 60 -100 0.1 1.0 (2.8) 115 2.25 20 0.01 24 120 910
-90
dB dB dB % % ppm/C dB Degrees % dB dB dB Vrms (V p-p) V kHz dB kHz dB s REV. PrA
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PRELIMINARY TECHNICAL DATA AD1835
Parameter ADC DECIMATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 48 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 96 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER, 192 kHz* Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation Group Delay DIGITAL I/O Input Voltage High Input Voltage Low Output Voltage High Output Voltage Low Leakage Current POWER SUPPLIES Supply Voltage (AVDD and DVDD) Supply Voltage (OVDD) Supply Current IANALOG Supply Current IANALOG, Power-Down Supply Current IDIGITAL Supply Current IDIGITAL, Power-Down Dissipation Operation, Both Supplies Operation, Analog Supply Operation, Digital Supply Power-Down, Both Supplies Power Supply Rejection Ratio 1 kHz, 300 mV p-p Signal at Analog Supply Pins 20 kHz, 300 mV p-p Signal at Analog Supply Pins
*Guaranteed by design. Specifications subject to change without notice.
Min
Typ 40 0.01 48 120 460
Max
Unit kHz dB kHz dB s
20 0.01 24 55 340 37.5 0.01 55.034 55 160 89.954 0.01 104.85 80 110 2.4 0.8 ODVDD - 0.4 0.4 10 4.5 3.0 5.0 84 55 64 1 740 420 320 280 -60 -50 5.5 DVDD 95 67 72 4
kHz dB kHz dB s kHz dB kHz dB s kHz dB kHz dB s V V V V A V V mA mA mA mA mW mW mW mW dB dB
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PRELIMINARY TECHNICAL DATA
AD1835-SPECIFICATIONS
TIMING
Parameter MASTER CLOCK AND RESET tMH MCLK High tML MCLK Low tPDR PD/RST Low SPI PORT tCCH tCCL tCCP tCDS tCDH tCLS tCLH tCOE tCOD tCOTS CCLK High CCLK Low CCLK Period CDATA Setup CDATA Hold CLATCH Setup CLATCH Hold COUT Enable COUT Delay COUT Three-State Min 15 15 20 40 40 80 10 10 10 10 15 20 25 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Comments
To CCLK Rising From CCLK Rising To CCLK Rising From CCLK Rising From CLATCH Falling From CCLK Falling From CLATCH Rising
DAC SERIAL PORT Normal Mode (Slave) tDBH DBCLK High DBCLK Low tDBL fDB DBCLK Frequency tDLS DLRCLK Setup DLRCLK Hold tDLH tDDS DSDATA Setup tDDH DSDATA Hold Packed 256 Modes (Slave) DBCLK High tDBH tDBL DBCLK Low DBCLK Frequency fDB tDLS DLRCLK Setup tDLH DLRCLK Hold DSDATA Setup tDDS tDDH DSDATA Hold ADC SERIAL PORT Normal Mode (Master) tABD ABCLK Delay ALRCLK Delay Low tALD tABDD ASDATA Delay Normal Mode (Slave) ABCLK High tABH tABL ABCLK Low fAB ABCLK Frequency tALS ALRCLK Setup tALH ALRCLK Hold Packed 256 Mode (Master) ABCLK Delay tPABD tPALD LRCLK Delay tPABDD ASDATA Delay
60 60 64 10 10 10 10 15 15 256 10 5 10 10
ns ns fS ns ns ns ns ns ns fS ns ns ns ns To DBCLK Rising From DBCLK Rising To DBCLK Rising From DBCLK Rising To DBCLK Rising From DBCLK Rising To DBCLK Rising From DBCLK Rising
25 5 10 60 60 64 5 15
ns ns ns ns ns
From MCLK Rising Edge From ABCLK Falling Edge From ABCLK Falling Edge
fS ns ns 20 5 10 ns ns ns To ABCLK Rising From ABCLK Rising From MCLK Rising Edge From ABCLK Falling Edge From ABCLK Falling Edge
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PRELIMINARY TECHNICAL DATA AD1835
Parameter TDM256 MODE (Master) tTBD BCLK Delay FSTDM Delay tFSD tTABDD ASDATA Delay tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold TDM256 MODE (Slave) fAB BCLK Frequency tTBCH BCLK High BCLK Low tTBCL FSTDM Setup tTFS tTFH FSTDM Hold ASDATA Delay tABDD DSDATA1 Setup tTDDS tTDDH DSDATA1 Hold TDM512 MODE (Master) tABDH BCLK Delay FSTDM Delay tFSD tTABDD ASDATA Delay tTDDS DSDATA1 Setup tTDDH DSDATA1 Hold TDM512 MODE (Slave) BCLK Frequency fAB tTBCH BCLK High tTBCL BCLK Low FSTDM Setup tTFS tTFH FSTDM Hold tTABDD ASDATA Delay DSDATA1 Setup tTDDS tTDDH DSDATA1 Hold AUXILIARY INTERFACE tAXDS AAUXDATA Setup tAXDH AAUXDATA Hold AUXBCLK Frequency fABP Slave Mode tAXBH AUXBCLK High AUXBCLK Low tAXBL tAXLS AUXLRCLK Setup tAXLH AUXLRCLK Hold Master Mode AUXLRCLK Delay tAUXLRCLK tAUXBCLK AUXBCLK Delay
Specifications subject to change without notice.
Min
Max 20 5 10
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Comments From MCLK Rising From BCLK Rising From BCLK Rising To BCLK Falling From BCLK Falling
15 15 256 min min min min min min 40 5 10 15 15 512 20 20 5 10 5 10 10 10 64 15 15 10 10 5 15 fS fS
max
To BCLK Falling From BCLK Falling From BCLK Rising To BCLK Falling From BCLK Falling From MCLK Rising From BCLK Rising From BCLK Rising To BCLK Falling From BCLK Falling
20
ns ns ns ns ns ns ns ns ns
To BCLK Rising From BCLK Rising From BCLK Rising To BCLK Rising From BCLK Rising To AUXBCLK Rising From AUXBCLK Rising
fS ns ns ns ns ns ns
To AUXBCLK Rising From AUXBCLK Rising From AUXBCLK Falling From MCLK Rising Edge
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PRELIMINARY TECHNICAL DATA AD1835
tMH
MCLK
tMCLK
tML
PD/RST
tPDR
Figure 1. MCLK and PD/RST Timing
TEMPERATURE RANGE
Parameter Specifications Guaranteed Functionality Guaranteed Storage
Min -40 -65
Typ 25
Max +85 +150
Unit C C C
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
AVDD, DVDD, OVDD to AGND, DGND . . . -0.3 V to +6.0 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . -0.3 V to ODVDD + 0.3 V Analog I/O Voltage to AGND . . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . . -40C to +85C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD1835AS
Temperature Range -40 C to +85 C
o o
Package Description 52-Lead MQFP
Package Option S-52
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1835 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PRELIMINARY TECHNICAL DATA AD1835
PIN CONFIGURATION
DSDATA4 DSDATA3 DSDATA2 DSDATA1 ASDATA ALRCLK
ODVDD
ABCLK
DGND
52 51 50 49 48 DVDD CLATCH CIN PD/RST AGND OUTLN1 OUTLP1 OUTRN1 OUTRP1
47 46 45 44 43 42 41 40 39 DVDD 38 DBCLK 37 DLRCLK 36 M/S 35 AGND
1 2 3 4 5 6 7 8 9
DGND
MCLK
COUT
CCLK
AD1835 TOP VIEW
(Not to Scale)
34 OUTRP4 33 OUTRN4 32 OUTLP4 31 OUTLN4 30 AGND 29 AVDD 28 OUTRP3 27 OUTRN3
AGND 10 AVDD 11 OUTLN2 12 OUTLP2 13 14 15 16 17 18 19 20 21 22 23 24 25 26
OUTRN2 AGND ADCRN ADCRP AGND OUTLN3 OUTRP2 OUTLP3 ADCLN AVDD ADCLP FILTD FILTR
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 39 2 3 4 5, 10, 16, 24, 30, 35 6, 12, 25, 31 7, 13, 26, 32 8, 14, 27, 33 9, 15, 28, 34 11, 19, 29 17 18 20 21 22 23 36 37 38 40, 52 41-44 45 46 47 48 49 50 51 REV. PrA
Mnemonic DVDD CLATCH CIN PD/RST AGND OUTLNx OUTLPx OUTRNx OUTRPx AVDD FILTD FILTR ADCLN ADCLP ADCRN ADCRP M/S DLRCLK DBCLK DGND DSDATAx ABCLK ALRCLK MCLK ODVDD ASDATA COUT CCLK
Input/ Output I I I O O O O
Description Digital Power Supply. Connect to digital 5 V supply. Latch Input for Control Data Serial Control Input Power-Down/Reset Analog Ground DACx Left Channel Negative Output DACx Left Channel Positive Output DACx Right Channel Negative Output DACx Right Channel Positive Output Analog Power Supply. Connect to analog 5 V supply. Filter Capacitor Connection. Recommended 10 F 100 nF. Reference Filter Capacitor Connection. Recommended 10 F 100 nF. ADC Left Channel Negative Input ADC Left Channel Positive Input ADC Right Channel Negative Input ADC Right Channel Positive Input ADC Master/Slave Select DAC LR Clock DAC Bit Clock Digital Ground DACx Input Data (Left and Right Channels) ADC Bit Clock ADC LR Clock Master Clock Input Digital Output Driver Power Supply ADC Serial Data Output Output for Control Data Control Clock Input for Control Data -7-
I I I I I I/O I/O I I/O I/O I O O I
PRELIMINARY TECHNICAL DATA AD1835-Typical Performance Characteristics
0
5 0 -5
MAGNITUDE - dB
0 5 10 FREQUENCY - Normalized to fS 15
-50
MAGNITUDE - dB
-10
-100
-15 -20
-150
-25 -30 0 5 10 FREQUENCY - Hz 15 20
TPC 1. ADC Composite Filter Response
TPC 4. ADC High-Pass Filter Response, fS = 96 kHz
5 0 -5
MAGNITUDE - dB
0
-50 -10 dB -15 -100 -20 -25 -30 0 5 10 FREQUENCY - Hz 15 20 -150 0
50
100 kHz
150
200
TPC 2. ADC High-Pass Filter Response, fS = 48 kHz
TPC 5. DAC Composite Filter Response, fS = 48 kHz
0
0
MAGNITUDE - dB
-50
dB
-50
-100
-100
-150 0 1.0 1.5 0.5 FREQUENCY - Normalized to fS 2.0
-150
0
50
100 kHz
150
200
TPC 3. ADC Composite Filter Response (Pass-Band Section)
TPC 6. DAC Composite Filter Response, fS = 96 kHz
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PRELIMINARY TECHNICAL DATA AD1835
0
0.2
0.1
-50
dB
dB
0 50 100 kHz 150 200
0
-100
-0.1
-150
-0.2
0
10
20 kHz
30
40
50
TPC 7. DAC Composite Filter Response, fS = 192 kHz
TPC 9. DAC Composite Filter Response, fS = 96 kHz (Pass-Band Section)
0.1
0.1
0.05
0.05
dB
0
dB
0
-0.05
-0.05
-0.1
0
5
10 kHz
15
20
-0.1
0
20
40 kHz
60
80
100
TPC 8. DAC Composite Filter Response, fS = 48 kHz (Pass-Band Section)
TPC 10. DAC Composite Filter Response, fS = 192 kHz (Pass-Band Section)
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PRELIMINARY TECHNICAL DATA AD1835
DEFINITIONS Dynamic Range Gain Drift
The ratio of a full-scale input signal to the integrated input noise in the pass band (20 Hz to 20 kHz), expressed in decibels (dB). Dynamic range is measured with a -60 dB input signal and is equal to (S/[THD + N]) +60 dB. Note that spurious harmonics are below the noise with a -60 dB input, so the noise level establishes the dynamic range. The dynamic range is specified with and without an A-Weight filter applied.
Signal to (Total Harmonic Distortion + Noise)
Change in response to a near full-scale input with a change in temperature, expressed as parts-per-million (ppm) per C.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a full-scale 1 kHz sine wave input on the other channel, expressed in decibels.
Power Supply Rejection
[S/(THD + N)] The ratio of the root-mean-square (rms) value of the fundamental input signal to the rms sum of all other spectral components in the pass band, expressed in decibels (dB).
Pass Band
With no analog input, signal present at the output when a 300 mV p-p signal is applied to power supply pins, expressed in decibels of full scale.
Group Delay
The region of the frequency spectrum unaffected by the attenuation of the digital decimator's filter.
Pass-Band Ripple
Intuitively, the time interval required for an input pulse to appear at the converter's output, expressed in milliseconds (ms). More precisely, the derivative of radian phase with respect to radian frequency at a given frequency.
Group Delay Variation
The peak-to-peak variation in amplitude response from equalamplitude input signal frequencies within the pass band, expressed in decibels.
Stop Band
The difference in group delays at different input frequencies. Specified as the difference between the largest and the smallest group delays in the pass band, expressed in microseconds (s).
GLOSSARY
The region of the frequency spectrum attenuated by the digital decimator's filter to the degree specified by stop-band attenuation.
Gain Error
ADC-Analog-to-Digital Converter DAC-Digital-to-Analog Converter DSP-Digital Signal Processor IMCLK-Internal Master Clock signal used to clock the ADC and DAC engines MCLK-External Master Clock signal applied to the AD1835
With a near full-scale input, the ratio of actual output to expected output, expressed as a percentage.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the two stereo channels, expressed in decibels.
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PRELIMINARY TECHNICAL DATA AD1835
(Continued from Page 1)
and a continuous-time voltage out analog section. Each DAC has independent volume control and clickless mute functions. The ADC comprises two 24-bit conversion channels with multibit sigma-delta modulators and decimation filters. The AD1835 also contains an on-chip reference with a nominal value of 2.25 V. The AD1835 contains a flexible serial interface that allows for glueless connection to a variety of DSP chips, AES/EBU receivers, and sample rate converters. The AD1835 can be configured in Left-Justified, Right-Justified, I2S-, or DSP-compatible serial modes. Control of the AD1835 is achieved by means of an SPI-compatible serial port. While the AD1835 can be operated from a single 5 V supply, it also features a separate supply pin for its digital interface that allows the device to be interfaced to other devices using 3.3 V power supplies. The AD1835 is available in a 52-lead MQFP package and is specified for the industrial temperature range of -40C to +85C.
FUNCTIONAL OVERVIEW ADCs
Each set of differential output pins sits at a dc level of VREF and swings 1.4 V for a 0 dB digital input signal. A single op amp third order external low-pass filter is recommended to remove high-frequency noise present on the output pins, as well as to provide differential-to-single-ended conversion. Note that the use of op amps with low slew rate or low bandwidth may cause high-frequency noise and tones to fold down into the audio band; care should be exercised in selecting these components. The FILTD pin should be connected to an external grounded capacitor. This pin is used to reduce the noise of the internal DAC bias circuitry, thereby reducing the DAC output noise. In some cases, this capacitor may be eliminated with little effect on performance.
DAC and ADC Coding
The DAC and ADC output data stream is in a two's complement encoded format. The word width can be selected from 16-bit, 20-bit, or 24-bit. The coding scheme is detailed in Table I.
Table I. Coding Scheme
Code 01111......1111 00000......0000 10000......0000
Clock Signals
Level +FS 0 (Ref Level) -FS
There are two ADC channels in the AD1835, configured as a stereo pair. Each ADC has fully differential inputs. The ADC section can operate at a sample rate of up to 96 kHz. The ADCs include on-board digital decimation filters with 120 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz operation). ADC peak level information for each ADC may be read from the ADC Peak 0 and ADC Peak 1 Registers. The data is supplied as a 6-bit word with a maximum range of 0 dB to -63 dB and a resolution of 1 dB. The registers will hold peak information until read; after reading, the registers are reset so that new peak information can be acquired. Refer to the register description for details on the format. The two ADC channels have a common serial bit clock and a left-right framing clock. The clock signals are all synchronous with the sample rate. The ADC digital pins, ABCLK and ALRCLK, can be set to operate as inputs or outputs by connecting the M/S pin to ODVDD or DGND, respectively. When the pins are set as outputs, the AD1835 will generate the timing signals. When the pins are set as inputs, the timing must be generated by the external audio controller.
DACs
The DAC and ADC engines in the AD1835 are designed to operate from a 24.576 MHz internal master clock (IMCLK). This clock is used to generate 48 kHz and 96 kHz sampling on the ADC and 48 kHz, 96 kHz, and 192 kHz on the DAC, although the 192 kHz option is only available on one DAC pair. The stereo replicate feature can be used to copy this DAC data to the other DACs if required. To facilitate the use of different MCLK values, the AD1835 provides a clock scaling feature. The MCLK scaler can be programmed via the SPI port to scale the MCLK by a factor of 1 (pass-through), 2 (doubling), or scaling by a factor of 2/3. The default setting of the MCLK scaler is 2, which will generate 48 kHz sampling from a 12.288 MHz MCLK. Additional sample rates can be achieved by changing the MCLK value. For example, the CD standard sampling frequency of 44.1 kHz can be achieved using an 11.2896 kHz MCLK. Figure 2 shows the internal configuration of the clock scaler and converter engines. To maintain the highest performance possible, it is recommended that the clock jitter of the master clock signal be limited to less than 300 ps rms, measured using the edge-to-edge technique. Even at these levels, extra noise or tones may appear in the DAC outputs if the jitter spectrum contains large spectral peaks. It is highly recommended that the master clock be generated by an independent crystal oscillator. In addition, it is especially important that the clock signal should not be passed through an FPGA or other large digital chip before being applied to the AD1835. In most cases, this will induce clock jitter due to the fact that the clock signal is sharing common power and ground connections with other unrelated digital output signals.
The AD1835 has eight DAC channels arranged as four independent stereo pairs, with eight fully differential analog outputs for improved noise and distortion performance. Each channel has its own independently programmable attenuator, adjustable in 1024 linear steps. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBLCK) clock. Alternatively, one of the "packed data" modes may be used to access all eight channels on a single TDM data pin. A stereo replicate feature is included where the DAC data sent to the first DAC pair is also sent to the other DACs in the part. The AD1835 can accept DAC data at a sample rate of 192 kHz on DAC 1 only. The stereo replicate feature can then be used to copy the audio data to the other DACs.
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PRELIMINARY TECHNICAL DATA AD1835
DAC ENGINE 48kHz/96kHz/192kHz INTERPOLATION FILTER - MODULATOR ANALOG OUTPUT DAC I/P DAC
CLOCK SCALING 1 MCLK 12.288MHz 2/3 2 IMCLK = 24.576MHz
ADC ENGINE 48kHz/96kHz OPTIONAL HPF DECIMATOR/ FILTER - MODULATOR ANALOG INPUT
ADC O/P
Figure 2. Modulator Clocking Scheme
tCLS
CLATCH
tCCP
tCCH tCCL
tCLH tCOTS
CCLK
tCOE
CIN D15 D14 D9
tCDS tCDH
D8 D0
COUT
D9
D8
D0
tCOD
Figure 3. Format of SPI Timing
RESET and Power-Down
PD/RST will power down the chip and set the control registers to their default settings. After PD/RST is de-asserted, an initialization routine will run inside the AD1835 to clear all memories to zero. This initialization lasts for approximately 20 LRCLK intervals. During this time, it is recommended that no SPI writes occur.
Power Supply and Voltage Reference
parallel combination of 10 F and 100 nF. The reference voltage may be used to bias external op amps to the common-mode voltage of the analog input and output signal pins. The current drawn from the VREF pin should be limited to less than 50 A.
Serial Control Port
The AD1835 is designed for 5 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 F should also be provided on the same PC board as the codec. For critical applications, improved performance will be obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by means of two ferrite beads in series with the bypass capacitor of each supply. It is important that the analog supply be as clean as possible. The internal voltage reference is brought out on the FILTR pin and should be bypassed as close as possible to the chip, with a
The AD1835 has an SPI-compatible control port to permit programming the internal control registers for the ADCs and DACs and for reading the ADC signal levels from the internal peak detectors. The SPI control port is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 16 bits wide. The maximum serial bit clock frequency is 12.5 MHz and may be completely asynchronous to the sample rate of the ADCs and DACs. Figure 3 shows the format of the SPI signal.
Serial Data Ports--Data Format
The ADC serial data output mode defaults to the popular I2S format, where the data is delayed by 1 BCLK interval from the edge of the LRCLK. By changing Bits 6 to 8 in ADC Control Register 2, the serial mode can be changed to Right-Justified (RJ), Left-Justified DSP (DSP), or Left-Justified (LJ). In the RJ mode, it is necessary to set Bits 4 and 5 to define the width of the data-word.
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PRELIMINARY TECHNICAL DATA AD1835
The DAC serial data input mode defaults to I2S. By changing Bits 5, 6, and 7 in DAC Control Register 1, the mode can be changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2. The word width defaults to 24 bits but can be changed by reprogramming Bits 3 and 4 in DAC Control Register 1.
Packed Modes
interface to a single SHARC DSP serial port, allowing a SHARC DSP to access all eight channels of analog I/O. In this special mode, many pins are redefined; see Table II for a list of redefined pins. The auxiliary and the TDM interfaces are independently configurable to operate as masters or slaves. When the auxiliary interface is set as a master, by programming the Aux Mode bit in ADC Control Register II, the AUXLRCLK and AUXBCLK are generated by the AD1835. When the auxiliary interface is set as a slave, the AUXLRCLK and AUXBCLK need to be generated by an external ADC as shown in Figure 13. The TDM interface can be set to operate as a master or slave by connecting the M/S pin to DGND or ODVDD, respectively. In master mode, the FSTDM and BCLK signals are outputs and generated by the AD1835. In slave mode, the FSTDM and BCLK are inputs and should be generated by the SHARC. Slave mode operation is available for 48 kHz and 96 kHz operation (based on a 12.288 MHz or 24.576 MHz MCLK) and master mode operation is available for 48 kHz only.
The AD1835 has a packed mode that allows a DSP or other controller to write to all DACs and read all ADCs using one input data pin and one output data pin. Packed Mode 256 refers to the number of BCLKs in each frame. The LRCLK is low while data from a left channel DAC or ADC is on the data pin and high while data from a right channel DAC or ADC is on the data pin. DAC data is applied on the DSDATA1 pin and ADC data is available on the ASDATA pin. Figures 7-10 show the timing for the packed mode. Packed mode is only available for 48 kHz and when the ADC is set as a master (M/S = 0).
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external stereo ADCs to be interfaced to the AD1835 to provide 8in/8-out operation. In addition, this mode supports glueless
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
LEFT-JUSTIFIED MODE - 16 BITS TO 24 BITS PER CHANNEL
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
12S MODE - 16 BITS TO 24 BITS PER CHANNEL
LRCLK BCLK SDATA MSB
LEFT CHANNEL
RIGHT CHANNEL
LSB
MSB
LSB
RIGHT-JUSTIFIED MODE - SELECT NUMBER OF BITS PER CHANNEL
LRCLK BCLK SDATA MSB LSB MSB LSB
DSP MODE - 16 BITS TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH IS 2 fS 3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE
Figure 4. Stereo Serial Modes
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PRELIMINARY TECHNICAL DATA AD1835
tABH
ABCLK
tABP
tABL tALS
ALRCLK tALH
ASDATA LEFT-JUSTIFIED MODE
MSB
MSB-1
ASDATA I2S-JUSTIFIED MODE
MSB
ASDATA RIGHT-JUSTIFIED MODE
MSB
LSB
Figure 5. ADC Serial Mode Timing
tDBH
DBCLK
tDBP
tDBL tDLS
DLRCLK tDLH
DSDATA LEFT-JUSTIFIED MODE
tDDS
MSB MSB-1
tDDH
DSDATA I2S-JUSTIFIED MODE
tDDS
MSB
tDDH
DSDATA RIGHT-JUSTIFIED MODE
tDDS
MSB
tDDS
LSB
tDDH
tDDH
Figure 6. DAC Serial Mode Timing
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REV. PrA
PRELIMINARY TECHNICAL DATA AD1835
LRCLK 256 BCLKs BCLK 32 BCLKs ADC DATA SLOT 1 LEFT SLOT 2 SLOT 3 SLOT 4 SLOT 5 RIGHT SLOT 6 SLOT 7 SLOT 8
MSB
MSB-1
MSB-2
Figure 7. ADC Packed Mode 256
LRCLK 256 BCLKs BCLK 32 BCLKs DAC DATA SLOT 1 LEFT 1 SLOT 2 LEFT 2 SLOT 3 LEFT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
MSB
MSB-1
MSB-2
Figure 8. DAC Packed Mode 256
tABH
ABCLK
tABP
DBCLK
tDBH
tABL tALS
ALRCLK
DLRCLK
tDBL tDLS
tALH
tDLH
tABDD
MSB MSB-1
DSDATA
tDDS
MSB MSB-1
ASDATA
tDDH
Figure 9. ADC Packed Mode Timing
Figure 10. DAC Packed Mode Timing
REV. PrA
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PRELIMINARY TECHNICAL DATA AD1835
Table II. Pin Function Changes in Auxiliary Mode
Pin Name ASDATA (O) DSDATA1 (I) DSDATA2 (I)/AAUXDATA1 (I) DSDATA3 (I)/AAUXDATA2 (I) DSDATA4 (I)/AAUXDATA3 (I) ALRCLK (O) ABCLK (O) DLRCLK (I)/AUXLRCLK(I/O)
I S Mode I S Data Out, Internal ADC I2S Data In, Internal DAC1 I2S Data In, Internal DAC2 I2S Data In, Internal DAC3 I2S Data In, Internal DAC4 LRCLK for ADC BCLK for ADC LRCLK In/Out Internal DACs
2
2
Aux Mode TDM Data Out to SHARC TDM Data In from SHARC AUX-I2S Data In 1 (from Ext. ADC) AUX-I2S Data In 2 (from Ext. ADC) AUX-I2S Data In 3 (from Ext. ADC) TDM Frame Sync Out to SHARC TDM BCLK Out to SHARC (FSTDM) AUX LRCLK In/Out. Driven by Ext. LRCLK from ADC in slave mode. In master mode, driven by MCLK/512. AUX BCLK In/Out. Driven by Ext. BCLK from ADC in slave mode. In master mode, driven by MCLK/8.
DBCLK (I)/AUXBCLK(I/O)
BCLK In/Out Internal DACs
FSTDM
BCLK TDM
MSB TDM MSB TDM
8TH CH
TDM INTERFACE
ASDATA1 TDM (OUT)
1ST CH
ASDATA
INTERNAL ADC L1
AUX_ADC L2
AUX_ADC L3
AUX_ADC L4
INTERNAL ADC R1
AUX_ADC R2
AUX_ADC R3
AUX_ADC R4
32
MSB TDM MSB TDM
8TH CH
DSDATA1 TDM (IN)
1ST CH
DSDATA1
INTERNAL DAC L1
INTERNAL DAC L2
INTERNAL DAC L3
INTERNAL DAC L4
INTERNAL DAC R1
INTERNAL DAC R2
INTERNAL DAC R3
INTERNAL DAC R4
32
AUX LRCLK I2S (FROM AUX ADC #1) AUX BCLK I2S (FROM AUX ADC #1) AAUXDATA1 (IN) (FROM AUX ADC #1) AAUXDATA2 (IN) (FROM AUX ADC #2)
LEFT
RIGHT
AUX - I2S INTERFACE
I2S - MSB LEFT
I2S - MSB RIGHT
I2S - MSB LEFT
I2S - MSB RIGHT
AAUXDATA3 (IN) (FROM AUX ADC #3)
I2S - MSB LEFT NOTE: AUX BCLK FREQUENCY IS 64
I2S - MSB RIGHT
FRAME RATE; TDM BCLK FREQUENCY IS 256
FRAME RATE.
Figure 11. Aux Mode Timing
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REV. PrA
PRELIMINARY TECHNICAL DATA AD1835
30MHz
FSYNC-TDM (RFS)
SHARC
SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN)
TFS (NC)
RxDATA
RxCLK
LRCLK ADC #1 SLAVE BCLK DATA MCLK
LRCLK ADC #2 SLAVE BCLK DATA MCLK DBCLK/AUXBCLK DLRCLK/AUXLRCLK LRCLK ADC #3 SLAVE BCLK DATA MCLK DSDATA2/AAUXDATA1 DSDATA3/AAUXDATA2 DSDATA4/AAUXDATA3 MCLK ASDATA FSTDM BCLK DSDATA1
AD1835 MASTER
Figure 12. AUX-Mode Connection to SHARC (Master Mode)
30MHz
FSYNC-TDM (RFS)
SHARC
SHARC IS ALWAYS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN)
TFS (NC)
RxDATA
RxCLK
LRCLK ADC #1 MASTER BCLK DATA MCLK
LRCLK ADC #2 SLAVE BCLK DATA MCLK DBCLK/AUXBCLK LRCLK ADC #3 SLAVE BCLK DATA MCLK DLRCLK/AUXLRCLK DSDATA2/AAUXDATA1 DSDATA3/AAUXDATA2 DSDATA4/AAUXDATA3 MCLK ASDATA FSTDM BCLK DSDATA1
AD1835 SLAVE
Figure 13. Aux Mode Connection to SHARC (Slave Mode)
REV. PrA
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TxDATA
12.288MHz
TxCLK
TxDATA
12.288MHz
TxCLK
PRELIMINARY TECHNICAL DATA AD1835
CONTROL/STATUS REGISTERS DAC Volume Control
The AD1835 has 15 control registers, 13 of which are used to set the operating mode of the part. The other two registers, ADC Peak 0 and ADC Peak 1, are read-only and should not be programmed. Each of the registers is 10 bits wide with the exception of the ADC peak reading registers which are 6 bits wide. Writing to a control register requires a 16-bit data frame to be transmitted. Bits 15 to 12 are the address bits of the required register. Bit 11 is a read/write bit. Bit 10 is reserved and should always be programmed to 0. Bits 9 to 0 contain the 10-bit value that is to be written to the register or, in the case of a read operation, the 10-bit register contents. Figure 3 shows the format of the SPI read and write operation.
DAC Control Registers
Each DAC in the AD1835 has its own independent volume control. The volume of each DAC can be adjusted in 1024 linear steps by programming the appropriate register. The default value for this register is 1023, which provides no attenuation, i.e., full volume.
ADC Control Registers
The AD1835 register map has five registers that are used to control the functionality and read the status of the ADCs. The function of the bits in each of these registers is discussed below.
ADC Peak Level
The AD1835 register map has 10 registers that are used to control the functionality of the DAC section of the part. The function of the bits in these registers is discussed below.
Sample Rate
These two registers store the peak ADC result from each channel when the ADC peak readback function is enabled. The peak result is stored as a 6-bit number from 0 dB to -63 dB in 1 dB steps. The value contained in the register is reset once it has been read, allowing for continuous level adjustment as required. Note that the ADC peak level registers use the six most significant bits in the register to store the results.
Sample Rate
These bits control the sample rate of the DACs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and 192 kHz are available. The MCLK scaling bits in ADC Control III should be programmed appropriately, based on the master clock frequency.
Power-Down/Reset
This bit controls the sample rate of the ADCs. Based on a 24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are available. The MCLK scaling bits in ADC Control III should be programmed appropriately based on the master clock frequency.
ADC Power-Down
This bit controls the power-down status of the DAC section. By default normal mode is selected, but by setting this bit, the digital section of the DAC stage can be put into a low-power mode, thus reducing the digital current. The analog output section of the DAC stage is not powered down.
DAC Data-Word Width
This bit controls the power-down status of the ADC section and operates in a similar manner to the DAC power-down.
High-Pass Filter
These two bits set the word width of the DAC data. Compact Disc (CD) compatibility may require 16 bits, but many modern digital audio formats require 24-bit sample resolution.
DAC Data Format
The ADC signal path has a digital high-pass filter. Enabling this filter will remove the effect of any dc offset in the analog input signal from the digital output codes.
Dither
The AD1835 serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes. Details of these interface modes are given in the Serial Data Port section of this data sheet.
De-Emphasis
Enabling the dither function will add a small amount of random charge to the sampling capacitors on the ADC inputs. This will eliminate the effect of any idle tones that could occur if there were no input signal present.
ADC Data-Word Width
These two bits set the word width of the ADC data.
ADC Data Format
The AD1835 provides built-in de-emphasis filtering for the three standard samples rates of 32.0 kHz, 44.1 kHz, and 48 kHz.
Mute DAC
The AD1835 serial data interface can be configured to be compatible with a choice of popular interface formats, including I2S, LJ, RJ, or DSP modes.
Master/Slave Auxiliary Mode
Each of the eight DACs in the AD1835 has its own independent mute control. Setting the appropriate bit will mute the DAC output. The AD1835 uses a clickless mute function that attenuates the output to approximately -100 dB over a number of cycles.
Stereo Replicate
When the AD1835 is operating in the auxiliary mode, the auxiliary ADC control pins, AUXBCLK and AUXLRCLK, that connect to the external ADCs, can be set to operate as a master or slave. If the pins are set in slave mode, one of the external ADCs should provide the LRCLK and BCLK signals.
ADC Peak Readback
Setting this bit copies the digital data sent to the stereo pair DAC1 to the three other stereo DACs in the system. This allows all four stereo DACs to be driven by one digital data stream. Note that in this mode DAC data sent to the other DACs is ignored.
Setting this bit enables ADC peak reading. See the ADC section for more information.
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REV. PrA
PRELIMINARY TECHNICAL DATA AD1835
Table III. Control Register Map
Register Address 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Register Name DACCTRL1 DACCTRL2 DACVOL1 DACVOL2 DACVOL3 DACVOL4 DACVOL5 DACVOL6 DACVOL7 DACVOL8 ADCPeak0 ADCPeak1 ADCCTRL1 ADCCTRL2 ADCCTRL3 Reserved
Description DAC Control 1 DAC Control 2 DAC Volume-Left 1 DAC Volume-Right 1 DAC Volume-Left 2 DAC Volume-Right 2 DAC Volume-Left 3 DAC Volume-Right 3 DAC Volume-Left 4 DAC Volume-Right 4 ADC Left Peak ADC Right Peak ADC Control 1 ADC Control 2 ADC Control 3 Reserved
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W
Width 10 10 10 10 10 10 10 10 10 10 6 6 10 10 10 10
Reset Setting (Hex) 000 000 3FF 3FF 3FF 3FF 3FF 3FF 3FF 3FF 000 000 000 000 000 Reserved
Table IV. DAC Control I FUNCTION DAC DataWord Width
Address
R/W
RES De-Emphasis
DAC Data Format
Power-Down Reset
Sample Rate
15, 14, 13, 12 11 0000 0
10 0
9, 8 00 = None 01 = 44.1 kHz 10 = 32.0 kHz 11 = 48.0 kHz
7, 6, 5 000 = I S 001 = RJ 010 = DSP 011 = LJ 100 = Pack Mode 256 101 = Reserved 110 = Reserved 111 = Reserved
2
4, 3 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved
2
1, 0 (48 kHz) (96 kHz) (192 kHz) (48 kHz)
0 = Normal 00 = 8 1 = Power-Down 01 = 4 10 = 2 11 = 8
Table V. DAC Control II FUNCTION Stereo Address R/W RES Reserved Replicate MUTE DAC OUTR4 OUTL4 OUTR3 OUTL3 OUTR2 OUTL2 OUTR1
OUTL1
15, 14, 13, 12 0001
11 0
10 0
9 0
8
7
6
5
4
3
2
1
0
0 = Off 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 0 = On 1 = Replicate 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute
REV. PrA
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PRELIMINARY TECHNICAL DATA AD1835
Table VI. DAC Volume Control Table VII. ADC Peak
FUNCTION Address 15, 14, 13, 12 0010 = DACL1 0011 = DACR1 0100 = DACL2 0101 = DACR2 0110 = DACL3 0111 = DACR3 1000 = DACL4 1001 = DACR4 R/W 11 0 RES 10 0 DAC Volume 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0000000000 = 1/1024 0000000001 = 2/1024 0000000010 = 3/1024 1111111110 = 1022/1024 1111111111 = 1023/1024 Address 15, 14, 13, 12
FUNCTION
R/W RES Six Data Bits 11 10 0 9, 8, 7, 6, 5, 4
Four Fixed Bits 3, 2, 1, 0
0010 = Left ADC 1 1011 = Right ADC
000000 = 0.0 dBFS 0000 000001 = -1.0 dBFS 000010 = -2.0 dBFS These four bits are always zero 111111 = -63.0 dBFS
Table VIII. ADC Control I FUNCTION Address R/W RES Dither Filter ADC Power-Down Sample Rate Reserved
15, 14, 13, 12 1100
11 0
10 0
9 0 = Disabled 1 = Enabled
8 0 = All Pass 1 = High-Pass
7 0 = Normal 1 = Power-Down
6 0 = 48 kHz 1 = 96 kHz
5, 4, 3, 2, 1, 0 0, 0, 0, 0, 0, 0 0, 0, 0, 0, 0, 0
Table IX. ADC Control II FUNCTION Address R/W RES RES Master/Slave Aux Mode ADC Data Format ADC DataWord Width Reserved ADC MUTE Right Left
15, 14, 13, 12 1101
11 0
10 0
9 0 = Slave 1 = Master
8, 7, 6 000 = I2S 001 = RJ 010 = DSP 011 = LJ 100 = Packed 256 101 = Reserved 110 = Auxiliary 256 111 = Auxiliary 512
5, 4 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = Reserved
3, 2 0, 0
1 0 = On 1 = Mute
0 0 = On 1 = Mute
Table X. ADC Control III FUNCTION Address R/W IMCLK RES RES Reserved Clocking Scaling ADC Peak Readback DAC Test Mode ADC Test Mode
15, 14, 13, 12 11 1110 0
10 0
9, 8 0, 0
7, 6 00 = MCLK 01 = MCLK 10 = MCLK 11 = MCLK 2 2/3 2
5
4, 3, 2
1, 0
0 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode 1 = Enabled Peak Readback All others reserved All others reserved
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REV. PrA
PRELIMINARY TECHNICAL DATA AD1835
CASCADE MODE Dual AD1835Cascade
The AD1835 can be cascaded to an additional AD1835 that, in addition to six external stereo ADCs, can be used to create a 32-channel audio system with 16 inputs and 16 outputs. The cascade is designed to connect to a SHARC DSP and operates in a time division multiplexing (TDM) format. Figure 14 shows the connection diagram for cascade operation. The digital interface for both parts must be set to operate in Auxiliary 512 mode by programming ADC Control Register II. AD1835 #1 is set as a master device by connecting the M/S pin to DGND, and AD1835 #2 is set as a slave device by connecting the M/S to DVDD. Both devices should be run from the same MCLK and PD/RST signals to ensure that they are synchronized.
With Device 1 set as a master, it will generate the frame-sync and bit clock signals. These signals are sent to the SHARC and Device 2 ensuring that both know when to send and receive data. The cascade can be thought of as two 256-bit shift registers, one for each device. At the beginning of a sample interval, the shift registers contain the ADC results from the previous sample interval. The first shift register (Device 1) clocks data into the SHARC and also clocks in data from the second shift register (Device 2). While this is happening, the SHARC is sending DAC data to the second shift register. By the end of the sample interval, all 512 bits of ADC data in the shift registers will have been clocked into the SHARC and been replaced by DAC data which is subsequently written to the DACs. Figure 15 shows the timing diagram for the cascade operation.
AUX ADC (SLAVE) AUX ADC (SLAVE) AUX ADC (SLAVE)
AUX ADC (SLAVE)
AUX ADC (SLAVE)
AUX ADC (SLAVE)
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
LRCLK
DOUT
DOUT
DOUT
DOUT
DOUT
AUXLRCLK AUXDATA1 AUXDATA2 AUXDATA3
AUXLRCLK AUXDATA1 AUXDATA2 AUXDATA3
AUXBCLK
AUXBCLK
AD1835 #1 (MASTER)
AD1835 #2 (SLAVE)
SHARC (SLAVE)
DRx RFSx RCLKx TFSx TCLKx DTx
ASDATA ALRCLK ABCLK
DSDATA
ASDATA ALRCLK ABCLK
DSDATA
Figure 14. Cascade
256 ABCLKs TFSx/ RFSx AD1835 #1 DACs DTx L1 L2 L3 L4 R1 R2 R3 R4 L1 L2 AD1835 #2 DACs L3 L4 R1 R2 R3 R4 256 ABCLKs
AD1835 #1 ADCs DRx L1 L2 L3 L4 R1 R2 R3 R4 L1 L2
AD1835 #2 ADCs L3 L4 R1 R2 R3 R4
ABCLK DTx DRx MSB MSB MSB-1 MSB-1 LSB LSB 32 ABCLKs DON'T CARE
Figure 15. Cascade Timing
REV. PrA
-21-
DOUT
BCLK
BCLK
BCLK
BCLK
BCLK
BCLK
PRELIMINARY TECHNICAL DATA AD1835
AUDIO INPUT 600Z 47 F + 5.76k 100pF NPO 5.76k 120pF NPO
11k 3.01k 11k 270pF NPO
OP275
68pF NPO
237
OP275
OUTLNx
ADCxN 1nF NPO 100pF NPO 1nF NPO
OUTLPx
VREF
604 2n2F NPO
AUDIO OUTPUT
5.76k
5.76k
560pF NPO 5.62k 15k 5.62k 150pF NPO
750k
OP275
237
ADCxP
VREF
Figure 16. Typical ADC Input Filter Circuit
Figure 17. Typical DAC Output Filter Circuit
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REV. PrA
PRELIMINARY TECHNICAL DATA AD1835
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
52-Lead MQFP (S-52)
0.096 (2.45) MAX 0.510 (12.95) 0.520 (13.20) SQ 0.530 (13.45)
39 40 27 26
0.037 (0.95) 0.031 (0.80) 0.026 (0.65) SEATING PLANE
0.307 (7.80) REF
TOP VIEW
(PINS DOWN)
0.398 (10.11) 0.394 (10.00) SQ 0.390 (9.91)
VIEW A
52 1
PIN 1 14 13
0.009 (0.23) 0.005 (0.13) 0.083 (2.10) 0.079 (2.00) 0.077 (1.95)
0.026 (0.65) BSC
0.015 (0.38) 0.009 (0.22) 7 0
0.010 (0.25) MIN COPLANARITY
VIEW A
ROTATED 90 CCW
REV. PrA
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